Hello 802.11 Gurus,
One of my friends is trying to convince me that he with a
team of 3 (inclduing himself) can design a IEEE 802.11 (WAN) compliant
IP in Verilog HDL (for digital design) (atleast the softcore, i.e. RTL, plus synthesis, Verification etc.)
starting from IEEE Specs within 12 weeks.
The average team expereince is 4 years (or 5 maximum) with hardly
any expereince on Ethernet etc. The team's Verilog strength is also
"moderate" - meaning not so great.
My question to you all experts is: "Is this a realistic schedule"? I
thought a minimum of 6 months is needed.
Thanks a lot for any suggestions (this information will be useful for
my another friend who is willing to join this group).
Sorry for off-topic, off-techincal post.
Kind Regards,
VLSI Engr.